130 lines
4.5 KiB
C++
130 lines
4.5 KiB
C++
// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of NVIDIA CORPORATION nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Copyright (c) 2008-2025 NVIDIA Corporation. All rights reserved.
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// Copyright (c) 2004-2008 AGEIA Technologies, Inc. All rights reserved.
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// Copyright (c) 2001-2004 NovodeX AG. All rights reserved.
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#ifndef PXG_SOLVER_KERNEL_INDICES_H
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#define PXG_SOLVER_KERNEL_INDICES_H
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namespace physx
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{
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#define PXG_USE_SHARED_MEMORY_PRE_PREP 0
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struct PxgKernelBlockDim
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{
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enum
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{
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//Constraint partition
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CONSTRAINT_PRE_PARTITION = 1024,
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CONSTRAINT_PARTITION = 1024,
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PRE_INTEGRATION = 128,
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//Constraint pre-preparation
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CONSTRAINT_PREPREP_BLOCK = 128,
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//Constraint preparation
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CONSTRAINT_PREPARE_BLOCK_PARALLEL = 64,
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ARTI_CONSTRAINT_PREPARE = 64,
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//Multi-block solver code
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ZERO_BODIES = 256,
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SOLVE_BLOCK_PARTITION = 64,
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CONCLUDE_BLOCKS = 256,
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WRITEBACK_BLOCKS = 256,
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WRITE_BACK_BODIES = 256,
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COMPUTE_BODIES_AVERAGE_VELOCITY = 256,
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//threshold stream
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INITIALIZE_INPUT_AND_RANKS = 256,
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RADIXSORT = 256,
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REORGANIZE_THRESHOLDSTREAM = 256,
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COMPUTE_ACCUMULATED_THRESHOLDSTREAM = 256,
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OUTPUT_ACCUMULATED_THRESHOLDSTREAM = 256,
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WRITEOUT_ACCUMULATEDFORCEPEROBJECT = 256,
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COMPUTE_EXCEEDEDFORCE_THRESHOLDELEMENT_INDICE = 256,
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OUTPUT_EXCEEDEDFORCE_THRESHOLDELEMENT_INDICE = 256,
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SET_THRESHOLDELEMENT_MASK = 256,
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COMPUTE_THRESHOLDELEMENT_MASK_INDICES = 256,
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OUTPUT_THRESHOLDELEMENT_MASK_INDICES = 256,
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CREATE_FORCECHANGE_THRESHOLDELEMENTS = 256,
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//Integration
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INTEGRATE_CORE_PARALLEL = 128,
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CLEAR_FRICTION_PATCH_COUNTS = 256,
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DMA_CHANGED_ELEMS = 512,
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COMPUTE_STATIC_CONTACT_CONSTRAINT_COUNT = 512
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};
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};
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struct PxgKernelGridDim
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{
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enum
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{
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//Constraint partition
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CONSTRAINT_PRE_PARTITION = 1,
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CONSTRAINT_PARTITION = 1,
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PRE_INTEGRATION = 64,
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//Constraint preparation
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CONSTRAINT_PREPREP_BLOCK = 128,
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CONSTRAINT_PREPARE_BLOCK_PARALLEL = 256,
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//Multi-block solver code
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ZERO_BODIES = 64,
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SOLVE_BLOCK_PARTITION = 64,
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CONCLUDE_BLOCKS = 64,
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WRITEBACK_BLOCKS = 64,
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WRITE_BACK_BODIES = 64,
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COMPUTE_BODIES_AVERAGE_VELOCITY = 128,
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//threshold stream
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INITIALIZE_INPUT_AND_RANKS = 64,
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RADIXSORT = 32, //this must be 32 to match the BLOCK_SIZE for the radix sort kernel
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REORGANIZE_THRESHOLDSTREAM = 64,
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COMPUTE_ACCUMULATED_THRESHOLDSTREAM = 32,//this must be 32 to match the BLOCK_SIZE for the compute kernel
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OUTPUT_ACCUMULATED_THRESHOLDSTREAM = 32,//this must be 32 to match the BLOCK_SIZE for the output kernel
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WRITEOUT_ACCUMULATEDFORCEPEROBJECT = 64,
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COMPUTE_EXCEEDEDFORCE_THRESHOLDELEMENT_INDICE = 32,
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OUTPUT_EXCEEDEDFORCE_THRESHOLDELEMENT_INDICE = 32,
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SET_THRESHOLDELEMENT_MASK = 64,
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COMPUTE_THRESHOLDELEMENT_MASK_INDICES = 32,
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OUTPUT_THRESHOLDELEMENT_MASK_INDICES = 32,
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CREATE_FORCECHANGE_THRESHOLDELEMENTS = 64,
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//Integration
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INTEGRATE_CORE_PARALLEL = 64,
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CLEAR_FRICTION_PATCH_COUNTS = 64,
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DMA_CHANGED_ELEMS = 64,
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};
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};
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}
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#endif
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