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#ifndef PXG_SOLVER_KERNEL_INDICES_H
#define PXG_SOLVER_KERNEL_INDICES_H

namespace physx
{

#define PXG_USE_SHARED_MEMORY_PRE_PREP 0

struct PxgKernelBlockDim
{
	enum
	{
		//Constraint partition
		CONSTRAINT_PRE_PARTITION						= 1024,
		CONSTRAINT_PARTITION							= 1024,

		PRE_INTEGRATION									= 128,

		//Constraint pre-preparation
		CONSTRAINT_PREPREP_BLOCK						= 128,

		//Constraint preparation
		CONSTRAINT_PREPARE_BLOCK_PARALLEL				= 64,

		ARTI_CONSTRAINT_PREPARE							= 64,
		
		//Multi-block solver code
		ZERO_BODIES										= 256,
		SOLVE_BLOCK_PARTITION							= 64,
		CONCLUDE_BLOCKS									= 256,
		WRITEBACK_BLOCKS								= 256,
		WRITE_BACK_BODIES								= 256,
		COMPUTE_BODIES_AVERAGE_VELOCITY					= 256,

		//threshold stream
		INITIALIZE_INPUT_AND_RANKS						= 256,
		RADIXSORT										= 256,
		REORGANIZE_THRESHOLDSTREAM						= 256,
		COMPUTE_ACCUMULATED_THRESHOLDSTREAM				= 256,
		OUTPUT_ACCUMULATED_THRESHOLDSTREAM				= 256,
		WRITEOUT_ACCUMULATEDFORCEPEROBJECT				= 256,
		COMPUTE_EXCEEDEDFORCE_THRESHOLDELEMENT_INDICE	= 256,
		OUTPUT_EXCEEDEDFORCE_THRESHOLDELEMENT_INDICE	= 256,
		SET_THRESHOLDELEMENT_MASK						= 256,
		COMPUTE_THRESHOLDELEMENT_MASK_INDICES			= 256,
		OUTPUT_THRESHOLDELEMENT_MASK_INDICES			= 256,
		CREATE_FORCECHANGE_THRESHOLDELEMENTS			= 256,

		//Integration
		INTEGRATE_CORE_PARALLEL							= 128,
		CLEAR_FRICTION_PATCH_COUNTS						= 256,
		DMA_CHANGED_ELEMS								= 512,
		COMPUTE_STATIC_CONTACT_CONSTRAINT_COUNT			= 512
	};
};

struct PxgKernelGridDim
{
	enum
	{
		//Constraint partition
		CONSTRAINT_PRE_PARTITION						= 1,
		CONSTRAINT_PARTITION							= 1,

		PRE_INTEGRATION									= 64,
		//Constraint preparation
		CONSTRAINT_PREPREP_BLOCK						= 128,

		CONSTRAINT_PREPARE_BLOCK_PARALLEL				= 256,	
		
		//Multi-block solver code
		ZERO_BODIES								= 64,
		SOLVE_BLOCK_PARTITION					= 64,
		CONCLUDE_BLOCKS							= 64,
		WRITEBACK_BLOCKS						= 64,
		WRITE_BACK_BODIES						= 64,
		COMPUTE_BODIES_AVERAGE_VELOCITY			= 128,

		//threshold stream
		INITIALIZE_INPUT_AND_RANKS						= 64,
		RADIXSORT										= 32, //this must be 32 to match the BLOCK_SIZE for the radix sort kernel
		REORGANIZE_THRESHOLDSTREAM						= 64,
		COMPUTE_ACCUMULATED_THRESHOLDSTREAM				= 32,//this must be 32 to match the BLOCK_SIZE for the compute kernel
		OUTPUT_ACCUMULATED_THRESHOLDSTREAM				= 32,//this must be 32 to match the BLOCK_SIZE for the output kernel
		WRITEOUT_ACCUMULATEDFORCEPEROBJECT				= 64,
		COMPUTE_EXCEEDEDFORCE_THRESHOLDELEMENT_INDICE	= 32,
		OUTPUT_EXCEEDEDFORCE_THRESHOLDELEMENT_INDICE	= 32,
		SET_THRESHOLDELEMENT_MASK						= 64,
		COMPUTE_THRESHOLDELEMENT_MASK_INDICES			= 32,
		OUTPUT_THRESHOLDELEMENT_MASK_INDICES			= 32,
		CREATE_FORCECHANGE_THRESHOLDELEMENTS			= 64,
		//Integration
		INTEGRATE_CORE_PARALLEL							= 64,
		CLEAR_FRICTION_PATCH_COUNTS						= 64,
		DMA_CHANGED_ELEMS								= 64,
	};
};

}  

#endif